AMD officially placed Zen 7 on its CPU roadmap for the first time during its Financial Analyst Day in November 2025. While the company shared little beyond confirming the architecture exists, leaker Moore’s Law Is Dead published detailed information around the same time, citing multiple sources with direct knowledge at AMD and close partners. The result is the most complete picture yet of what AMD is planning, and it points to a fundamental shift in how the company designs its chiplets.
Since Zen 2 launched in 2019, every AMD Core Complex Die (CCD) has housed exactly eight cores. Zen 3, Zen 4, and Zen 5 all maintained that same design. Zen 7, codenamed “Grimlock,” is reportedly breaking that pattern with a new 16-core chiplet codenamed “Silverton,” manufactured on TSMC’s A14 (1.4nm) process. The die is estimated at 98mm², significantly larger than current Ryzen chiplets.
For the lower end of the lineup, AMD is also said to be preparing a smaller 8-core chiplet codenamed “Silverking,” measuring around 56mm², targeting budget models and mobile processors. The desktop version of these processors, codenamed “Grimlock Ridge,” is reportedly still targeting the AM5 socket, meaning users with existing DDR5 motherboards would be able to upgrade without platform changes, extending AM5 compatibility across what would be four consecutive Zen generations.
Beyond core count, each Zen 7 core is set to double its L2 cache from 1MB to 2MB per core. Intel’s Raptor Lake already uses 2MB of L2 per core, a design decision that contributed to its strong gaming performance. According to MLID’s sources, this cache increase alone is projected to deliver around 8% IPC improvement over Zen 6, with total architectural gains estimated between 15% and 25% in single-threaded performance compared to Zen 6.
16 cores, 224MB of cache, and what it means for gaming
The cache configuration for Zen 7’s 16-core chiplet is substantial. Each CCD will carry 64MB of on-die L3 cache, double what current 8-core chiplets provide. AMD is also planning a 160MB 3D V-Cache die, manufactured on TSMC’s N4P process, which will sit underneath the core die in X3D variants. Combined, a single 16-core Zen 7 CCD with V-Cache would carry 224MB of L3 cache. In a dual-CCD desktop configuration, that figure reaches 448MB total.
The current Ryzen 7 9800X3D, which leads gaming benchmarks today, has 96MB of L3 cache, less than half of what a single Zen 7 X3D chiplet would offer.
Games are highly sensitive to cache availability. More L3 cache reduces how frequently the CPU needs to access system RAM, which translates to lower frame latency and more consistent frametimes, particularly in CPU-demanding titles. AMD’s existing X3D chips already demonstrate this advantage clearly, with the 9800X3D posting measurable gains in 1% lows and frame pacing over non-X3D counterparts.
According to the MLID leak, Zen 7’s V-Cache implementation is also expected to deliver around 20% performance improvement in non-gaming workloads, a meaningful departure from previous X3D generations, where the extra cache benefited gaming almost exclusively.
The 8-core Silverking chiplet reportedly will not support 3D V-Cache, which would effectively limit X3D variants to the higher-end 16-core parts. That would mean the end of budget-friendly X3D options like the Ryzen 5 7600X3D in the Zen 7 generation.
A larger die, a smarter platform play
The decision to move to a physically larger chiplet carries economic logic at advanced nodes. At 1.4nm, TSMC’s A14 process delivers substantially higher transistor density than previous generations, meaning a 98mm² die at that node contains far more compute capability than the same area at 5nm or 7nm would. Additionally, fitting 16 cores on a single CCD eliminates the inter-chiplet latency that affects multi-CCD configurations.
In current processors like the Ryzen 9 9950X3D, only the CCD with V-Cache benefits fully from the extra cache, cores on the second chiplet must access it through the I/O die, adding latency. A single 16-core CCD avoids that problem entirely: all cores have equal, direct access to the L3 pool and the V-Cache die.
The desktop Zen 7 “Grimlock Ridge” processors will also reuse the same I/O die planned for Zen 6’s “Olympic Ridge” desktop lineup, extending platform continuity and reducing engineering costs. A flagship 32-core dual-CCD Zen 7 configuration would not be surprising at a price point around $999, given the silicon area and manufacturing costs involved at TSMC’s most advanced nodes.
EPYC Zen 7 server processors, codenamed “Steamboat” and “Verano,” are currently estimated to launch in the first half of 2028, with Ryzen desktop and mobile variants likely following before the end of that year. As with all pre-announcement information, these specifications remain unverified until AMD makes an official disclosure, and details are subject to change.
That said, the direction AMD appears to be heading, bigger chiplets, more cache, platform longevity, lines up closely with the competitive pressures the company faces from Intel’s upcoming Nova Lake architecture, which is also said to target high cache capacities for gaming performance.
So, what do you think about AMD going bigger with its chiplets? Are you already planning your Zen 7 upgrade on your current AM5 board, or does the potential $999 price tag make you want to stick with your 9800X3D for another generation? Drop your thoughts in the comments, we want to know where you stand!